One or more aspects of the present invention relate generally to clock management circuits for digital systems and, more particularly, to phase detection using asynchronous level-mode sequential circuitry.
Clock management circuits are used in integrated circuit (IC) devices, such as field programmable gate arrays (FPGAs), to control timing of various clock signals therein. For example, clock management circuits can be used to compensate for skewing in a clock signal as the clock signal propagates within or between IC devices. Clock skew is caused by various factors, such as capacitive and resistive loading on the clock line, and propagation delay.
Clock management is often performed using phase-lock loop (PLL) or delay-lock loop (DLL) circuits. In general, PLL and DLL circuits are used to synchronize the frequency and/or phase of an output clock signal to that of an input clock signal. PLL and DLL circuits employ phase detectors to determine how much and in what direction the frequency and/or phase of the output clock signal should be adjusted relative to the input clock signal. In fully-digital clock management systems, it is desirable for the phase detector to remain stable in between phase detection operations.
Known phase detectors, however, are deleteriously affected by undesired jitter in the clock signals. Such jitter is typically caused by local noise within the clock management circuit, as well as external noise within the IC device. Phase detectors are also susceptible to mismatch among their various constituent components.
Accordingly, it would be both desirable and useful to provide an improved phase detector for use with clock management circuits in IC devices.
A phase detector employing asynchronous level-mode sequential circuitry is provided in accordance with one or more aspects of the present invention. The phase detector comprises edge detection circuitry for generating a first edge detection signal and a second edge detection signal. The first edge detection signal is indicative of an edge in a first clock signal, and the second edge detection signal is indicative of an edge in a second clock signal. The phase detector further includes a state machine that is asynchronously responsive to level changes in the first and second edge signals. The state machine generates a control signal indicative of which of the first and second clock signals is leading the other of the first and second clock signals.